The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, it relates an electrostatic discharge protection circuit for multi-power and mixed-voltage integrated circuit.
In recent year, semiconductor components are widely used in the area of industry, commerce, residence, communication, traffic and electric power. In future, the trend of the electric components and electronics industry will be towards integrated circuit and high voltage, high current power, less switch module. However, there is a problem of electrostatic discharge in the integrated circuit yet. The damage caused by static electronics to the integrated circuit is a very serious issue. Especially, as the technology is getting progress, the techniques that are used to improve the operation speed of circuits such as short channel length, thinner gate oxides, utilization of polyside and silicide, as well as the techniques to reduce the Hot-carrier effects dramatically degrade the barring ability of ESD circuits.
Separate power is used widely in integrated circuit in order to avoid the noise coupling between the buses. However, the protection of ESD will be weak because of using separate power. Please refer to FIG. 1, which shows a circuit diagram of the conventional ESD protection of separate power. In FIG. 1, the circuit is consisted of two pairs of separate power. One pair is the first output power 60 and the first input power 70. Another pair is the second output power 80 and the second input power 90. If the ESD pulse is applied to the pin 10 with respect to the first input power 70, the ESD current may discharge through the ESD protection device 50 along the first path 20, which is the desired one for ESD current to go. However, there is resistance 100 on the way of the first path 20 which is between the second input power 90 and the second output power 80. For integrated circuit, according to the formula of electric circuit: resistance multiplied by current is voltage. Thus, the resistance 100 may be large enough to introduce a large voltage drop. Therefore, there is a large voltage difference between the pin 10 and the first input power 70. If the voltage difference is too large, some internal circuit will be overstressed and then damaged because the ESD current is discharged along the unexpected second path 30.
Please refer to FIG. 2, which shows a circuit diagram of another conventional ESD protection of separate power. If there is a first ESD protection cell 110 connected to the first output power 60 and the first input power 70, the ESD current may be discharged through the third path 130. Similarly, if there is the second ESD protection cell 120 connected to the second output power 80 and the second input power 90, the ESD current may be discharged through the forth path 140. By using this design, the internal circuit can be protected from the overstress so the ESD protection cell is very important in separate power.
In the conventional technique, back-to-back diode or diode-connected device is always used to serve as this kind of ESD protection cell. As shown in FIG. 3, there is an internal circuit diagram of a conventional ESD protection cell. In the FIG. 3, a group of diodes 205 in back-to-back mode is used to connect the first power 201 and the second power 203. As shown in FIG. 4, there is an internal circuit diagram of another conventional ESD protection cell. In the FIG. 4, a group of Metal Oxide Semiconductor (MOS) 216 is used to connect the first power 212 and the second power 214.
In the design of ESD protection cell, the number of back-to-back diode or diode-connected device is depended on the requirement of noise immunity and the voltage difference between the first power and the second power. To enhance the noise immunity, more diode is needful. If the voltage difference is too large, more diode is needful to protect the circuit. However, the protection efficiency of the ESD protection cell will be degraded by the increased diode number between different powers. Moreover, because of the dependent character of power, the voltage drop at the ESD protection cell will be larger if more back-to-back diode or diode-connected device is used in the ESD protection cell. Thus, this is another problem in design.
Nowadays, many different power supplies may be needful in many integrated circuits for different internal circuitry and for capability of independent operation. Based on the requirement of changing operational dynamically, each internal circuit is controlled by independent power. For example, referring to FIG. 2, during power saving mode, if the first input power 70 is deactivated independently, the power from the first output power 60 energized will flow to the de-energized first input power 70 through the conventional ESD protection cells such as those in FIG. 3 or FIG. 4 so the first input power 70 are also energized undesirably. According to the example above, current may flow from an energized power to a de-energized power so that power saving mode is defeated therefore spending power. Furthermore, the internal circuit may be damaged by a short circuit.
In view of the background of the invention described above, if the conventional ESD protection device is used in the multi-power and mixed-voltage circuit, the interference will happen between each power so that the independent operation of each power will be defeated. Then, spending power is induced because the power of circuit is out of control undesirably. Supposing for enhancing the noise immunity between each power, a large number of diode or MOS are acceded into the conventional ESD protection device. However, the ESD protection efficiency of power will be degraded. Otherwise, considering the character of diode in use and calculating the number of diode in use accurately are required if using the conventional ESD protection device in circuit. Therefore, the difficulty and complication of circuit design will increase.
It is the principal object of this invention to provide an ESD protection circuit for efficient quarantine between each power to solve the problem, which is the circuit efficiency affected by the dependent operation of power due to the mutual influence between each power when the conventional ESD protection circuit is used.
In accordance with the aforementioned objects of this invention, the invention provides an ESD protection circuit to distinguish between the voltage of ESD and the normal operation voltage of power and let the power is out of the outside influence and operates independently. The ESD protection circuit of this invention is consisted of: an ESD protection cell further comprising: a transistor; a control circuit connected with the gate of the transistor electrically; a voltage selector and one point of the voltage selector connected with the control circuit electrically to output a voltage signal to the control circuit. And an ESD bus connected with the transistor and the voltage selector of the ESD protection cell electrically. The voltage selector of the ESD protection cell connects the power and the ESD bus. One of the drain and the source of the transistor of the ESD protection cell is connected with the power and another one is connected with the ESD bus.